Energy efficient hybrid adder architecture |
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| Affiliation: | 1. Technion, EE Faculty, Haifa, Israel;2. Bar-Ilan University, Engineering Faculty, Ramat-Gan, Israel;3. Intel Corporation, Haifa, Israel;1. School of Computer Science and IT, RMIT University, Victoria, Australia;2. School of Computer Science, University of Oklahoma, Norman, OK 73019-6151, USA;1. Dept. of ECE, SRM University, Chennai, India;2. ECE Dept. Saveetha Engineering College, Chennai, India;1. Université Pierre et Marie Curie, 4 Place Jussieu, 75252 Paris, France;2. CEA, DAM, DIF, F-91297 Arpajon, France;1. National Chung Cheng University, Chiayi 621, Taiwan;2. Synopsys, Inc., Hsinchu 300, Taiwan |
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| Abstract: | An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool. |
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| Keywords: | Adders Hybrid adders Low-energy VLSI design |
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