Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage |
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| Affiliation: | 1. Electronics Engineering Department, Bani-Suef University, Bani-Suef, Egypt;2. Mentor Graphics Corporation, Cairo, Egypt;3. Electrical Engineering Department, Minia University, El-Minia, Egypt;1. Guangzhou Institute of Advanced Technology, CAS, China;2. Shenzhen Institute of Advanced Technology, CAS, China;3. The Chinese University of Hong Kong, China;4. University of Nevada, Las Vegas, United States;5. University of Turku, Finland;6. Royal Institute of Technology, Sweden;1. Department of Computer Science and Technology, Beijing University of Chemical Technology, No.15, Beisanhuan East Road, ChaoYang District, Beijing 100029, China;2. Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;3. Department of Electronic and Communication Engineering, School of Electrical and Electronic Engineering, North China Electric Power University, Baoding 071003, China;4. School of Computer and Information, Hefei University of Technology, Hefei 230009, China;1. School of Electrical and Computer Engineering, University of Tehran, Iran;2. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Iran;3. Department of Electrical Engineering-Systems, University of Southern California, USA |
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| Abstract: | Three-dimensional integration technology is proposed to break down long wires and increase integration level of emerging complex designs. However, efficiency of this technology heavily depends on the usage of Through-Silicon Vias. TSVs are key solutions for cooling the 3D-chips but they occupy considerable silicon area. Therefore, reducing the number of required TSVs in routing step is very critical in 3D-chips. In this paper, a TSV multiplexing approach is proposed to reduce the number of required routing TSV. We proposed two multiplexed 3D-switchbox architectures. In the first architecture, the TSVs inside the switchboxes are multiplexed while in the second architecture, TSVs are multiplexed between the switchboxes. Moreover, a routing algorithm is suggested to route the FPGA using the multiplexed switchboxes to evaluate the proposed architectures. Experimental results show that the presented architectures and algorithms reduce the number of used TSVs by 64.58% and 71.27% on average for the first and second architectures respectively, in cost of a negligible overheads in total wire length and auxiliary switches. |
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| Keywords: | Multiplexing Switchbox Three-dimensional FPGA |
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