Aging analysis of nMOS of a 1.3-μm partially depleted SIMOX SOItechnology comparison with a 1.3-μm bulk technology

Hot carrier degradation of nMOS of a 1.3-μm partially depleted rad-hard SOI CMOS technology is analyzed in detail. The relative importances of the maximum electric field, the localization of the trapped charges, and the LDD structure are pointed out through two-dimensional simulations and systematic comparisons with a 1.3-μm CMOS bulk technology. It is shown that the higher degradation rate of the SOI technology logically results from the contradictory constraints between rad-hardness (low-temperature process) and hot carrier resistance requirements. An annealing scheme comparable to the bulk one would lead to similar degradations