一种1750A指令集仿真软核设计与验证

MIL-STD-1750A指令集是星载弹载计算机常用指令集之一，为实现该类指令集CPU+FPGA的通用性验证，实现安全性、强度、单粒子翻转等异常测试，满足测试覆盖率要求，保证星载弹载计算机系统可靠性，提出了一种CPU+FPGA的仿真模型搭建方法，利用如中断和故障处理机制的实现、浮点运算单元设计方式、异常注入机制设计以及图形控制界面等关键技术，实现了一种精简1750A仿真软核。实验证明，利用该仿真软核设计的CPU+FPGA的仿真模型平台，可极大提高1750系列CPU相关接口的FPGA产品的验证效率和可靠性，也为后续星载弹载软件的测试提供了一套故障注入方便、故障定位清晰的测试平台。

Design and verification of a 1750A instruction set simulation soft core

Mil-std-1750a instruction set is one of the common instruction sets of satellite-borne missile computer. In order to realize the universality verification of CPU+FPGA of this kind of instruction set, realize the abnormal testing of safety, strength and single particle flip, meet the requirements of test coverage and ensure the reliability of satellite-borne and missile-borne computer system,A simulation model construction method of CPU+FPGA is proposed, and a simplified 1750A simulation soft core is realized by using key technologies such as the implementation of interrupt and fault processing mechanism, floating point operation unit design, anomaly injection mechanism design and graphical control interface.Experiments show that the simulation model platform of CPU+FPGA designed by using the simulation soft core can greatly improve the verification efficiency and reliability of FPGA products related to 1750 series CPU interfaces, and also provide a test platform for convenient fault injection and clear fault location for subsequent tests of satellite-borne and missile-borne software.