| 基于FPGA的UART IP核的设计实现 |
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| 引用本文： | 赵海登,刘晓文,胡景军,汤晓蕾. 基于FPGA的UART IP核的设计实现[J]. 通信技术, 2009, 42(5): 177-179 |
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| 作者姓名： | 赵海登 刘晓文 胡景军 汤晓蕾 |
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| 作者单位： | 1. 中国矿业大学,信息与电气工程学院,江苏,徐州,221008
2. 中国石化浙江金嘉湖油品储运分公司,浙江,嘉兴,314033 |
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| 基金项目： | 国家高技术研究发展计划(863计划) |
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| 摘 要： | 随着IC设计技术的发展，IP已经成为SOC设计的关键技术，利用已有IP可大大提高SOPC设计的效率和能力。UART是广泛使用的串行数据通信电路，一般说来，该接口由硬件（UART专用芯片）实现。采用VerilogHDL语言，结合有限状态机的设计方法来实现UART的IP核，将其核心功能集成到FPGA上，使整体设计紧凑、小巧，实现的UART功能稳定、可靠。
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| 关 键 词： | 现场可编程门阵列 UART IP Verilog硬件描述语言 |
Design and Implementation of UART IP Kernel Based on FPGA |
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| ZHAO Hai-deng,LIU Xiao-wen,HU Jing-jun,TANG Xiao-lei. Design and Implementation of UART IP Kernel Based on FPGA[J]. Communications Technology, 2009, 42(5): 177-179 |
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| Authors: | ZHAO Hai-deng LIU Xiao-wen HU Jing-jun TANG Xiao-lei |
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| Affiliation: | ZHAO Hai-deng, LIU Xiao-wen, HU Jing-jun, TANG Xiao-lei (①Schlool of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou Jiangsu 221008, China; ②Zhejiang Jinjiahu Oil Storage and Transportation Company, China Petroleum ＆ Chemical Corporation, Jiaxing Zhejiang314033, china) |
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| Abstract: | With the development of IC design technology, IP has become the key technology for SOC design, and it could greatly improve the efficiency and ability of the SOPC design. UART is a widely-used serial communication circuit, and generally implemented by specific UART chip. This UART IP kernel is implemented with VerilogHDL, and the main functions are integrated on FPGA by combining the design technique of finite state machine, thus making the structure compact and small, the function of VART IP kernel reliable and stable. |
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| Keywords: | UART IP |
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