基于FPGA的多接口转换研究与实现

主要研究多路串行数据同时接收/发送,然后汇合成一路串行数据发送/接收的多串口转换技术。使用Verilog语言在FPGA上实现了该方案,分别设计了数据的接收模块、发送模块、缓存模块以及系统的分频模块、延迟模块,实现了多路串行数据在通信速率互不影响的情况下合成一路高速串行数据收发的功能。通过Quartus II仿真和实验测试验证了该设计的可行性。在PC测试中,16路波特率为4 800 bit/s的串行数据,可以以波特率为115 200 bit/s进行聚合,各路数据速率无互相影响,且误码率为0。该设计的优点在于节约硬件开支,达到串口多用的效果,适用于多路数据同时采集的实时监控系统。

Research and Implementation of Multi-Interface Conversion Based on FPGA

This paper studies the multi-serial conversion technology, which can simultaneous reception of multiple serial data, and then send the merged data in one serial. This design is using Verilog language above the FPGA, We have designed the data receiver module, data transmission module, data cache module and frequency module, delay module, which can used to merge the data into one serial with no affect on the data rata. The feasibility of this design has been verified by the simulation on Quartus II and actual PC test. In the PC test, 16 groups data with 4800Hz baud rata can be send with 115200Hz baud rata with no affect, and the error rata is 0. The advantage of this design is saving the expenses of the hardware, and can use the serial effectively, which is applied to current affairs monitoring of multiple data.