| 基于FPGA的18b20的CRC校验码的并行算法及实现 |
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| 引用本文： | 张锦鹏,程明,王俊山.基于FPGA的18b20的CRC校验码的并行算法及实现[J].计算机与数字工程,2011,39(4):44-46. |
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| 作者姓名： | 张锦鹏 程明 王俊山 |
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| 作者单位： | 郑州大学信息工程学院,郑州,450001 |
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| 摘 要： | 在分析串行结构的CRC生成算法的基础上,研究了一种高效的8位并行CRC-8校验码生成算法。并且采用FPGA器件与Verilog语言,实现了18b20的56位地址码的CRC-8的校验模块。
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| 关 键 词： | 并行算法 18b20 CRC-8 Verilog FPGA |
Inplementation of the Parallel Algorithm of CRC Check Cooles in 18b20 Based on FPGA |
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| Zhang Jinpeng,Cheng Ming,Wang Junshang.Inplementation of the Parallel Algorithm of CRC Check Cooles in 18b20 Based on FPGA[J].Computer and Digital Engineering,2011,39(4):44-46. |
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| Authors: | Zhang Jinpeng Cheng Ming Wang Junshang |
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| Affiliation: | Zhang Jinpeng Cheng Ming Wang Junshang(Information Engineering College of Zhengzhou University,Zhengzhou 450001) |
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| Abstract: | Based on analysis of the structure of serial CRC generation algorithm,an efficient parallel 8-bit CRC-8 generation algorithm is studied in the paper.And CRC-8 checksum module of 18B20 56bit address is achieved with FPGA and Verilog language. |
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| Keywords: | parallel algorithm 18b20 CRC-8 Verilog FPGA |
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