CAD navigation and diagnostics by linking ATE and EDA

This paper describes a specific methodology and software that links automated test equipment (ATE) and electronic design automation (EDA) tools to identify and diagnose failures at the layout level. The ATE software, named wafer fail layout map (WFLMAP), works in concert with the EDA integrated circuits (IC) design database and provides computer-aided design (CAD) navigation and correlation between the tester failure data and IC design data. With this approach, layout-level defect diagnosis is achieved at the individual chip level, as well as at the wafer level. This method can also be used for improved design for manufacturing (DFM).