Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding |
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Authors: | Rizwan Asghar Di Wu Johan Eilert Dake Liu |
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Affiliation: | 1.Department of Electrical Engineering,Link?ping University,Link?ping,Sweden |
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Abstract: | This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully
re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for
error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple
iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the
interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts.
The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for
different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches
like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and
consumes 0.085 mm2 area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus
providing significant support to higher throughput systems based on parallel SISO processors. |
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