基于可重构FPGA技术的自适应FIR滤波器的实现

有限冲激响应(FIR)滤波器设计遇到的难题是滤波要进行大量乘法运算,即使是在全定制的专用集成电路中也会导致过大的面积与功耗.对于用硬件实现系数是常量的专用滤波器,可以通过分解系数变为应用加、减和移位而实现乘法.FIR滤波器的复杂性主要由用于系数乘法的加法器/减法器的数量决定.而对于自适应FIR滤波器,大多数场合下可用数字信号处理器(DSP)或CPU通过软件编程的方法来实现,但是对于要求高速运算的场合,VLSI实现是很好的选择.基于这一考虑,可以用符号数的正则表示(CSD)码表示系数, 再利用可重构现场可编程门阵列(FPGA)技术实现.可重构结构的应用,能保证系统的其余部分同时处于运行状态时实现FIR滤波器系数的更新.文中利用CSD码和可重构思想,提出了用FPGA实现自适应FIR滤波器的一种方案.

Implementation of Adaptive FIR Filter Based on Reconfigurable FPGAs

The complexity of FIR filters design is that there are a big number of multiplications, even with a completely customed ASIC there would be a big area and power consumptior. The implementation with hardware of finite impulse response (FIR) filters of constant-coefficient can use shifters, adders and subtracters to realize multiplication and the complexity is determined by the adder/subtracters. Adaptive FIR filters are most commonly implemented as a software process running on a digital signal processor (DSP) or CPU, but it is a good choice of implementation with VLSI. So, adaptive FIR filter can be implemented with CSD code and reconfigurable FPGAs. This article presents a solution to implement adaptive constant coefficient FIR filters based on reconfigurable and FPGAs.