不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.

Investigation on the Hot-Carrier-Induced Degradation for 1. 8V pMOS Under D ifferent Gate Voltage Stresses

According to the experimental measurement results,combining with the technology computer aided design (TCAD)simulations,the hot-carrier degradations of 1. 8V pMOS under different gate voltages are investigated in this pa-per.The results show that,with the gate voltage increasing,the electron injection mechanism changes to the hole injection mechanism,leading to the increases of the saturation drain current (Idsat ),linear drain current (Idlin )and threshold voltage (Vth ).However,because there is not any carrier injection,the degradation trend begins to change at Vgs =90%*Vds .More-over,the study also discovers that the generated interface states have more impact on the hole mobility in the depletion region than that in the non-depletion region.As a result,the degradation of forward Idsat is bigger than the degradation of reverse Idsat .However,the degradations of forward Idlin and reverse Idlin are same since the whole channel is not depleted under Idlin condition.