Material and process challenges in 100 nm interconnects module technology and beyond

In order for ultra-large-integrated (ULSI) circuits manufacturing to minimize the Cost of Ownership (CoO) aspect in the wiring process and realize fabricating semiconductor devices over 100 nm node, several Cu/low-k wiring technologies have been proposed. The evidential criteria in choosing the most probable one are physical or material limitation and requirements from manufacturing. A development of module processes (e.g., processing from low-k dielectrics to metal CMP) with proven equipment and material is an appropriate approach and has a high potential in overcoming those difficulties. In this paper, an advantage of dual Damascene Cu wiring accompanied with low-k (dielectric constant ∼2.7) and prediction of 100 nm Cu wiring module will be discussed.