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Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic
Authors:Christian Pacha  Oliver Kessler  Peter Glo¨seko¨tter  Karl F. Goser  Werner Prost  Andreas Brennemann  Uwe Auer  Franz J. Tegude
Affiliation:(1) Lehrstuhl Bauelemente der Elektrotechnik, Universita¨t Dortmund, D-44221 Dortmund, Germany;(2) Lehrstuhl Bauelemente der Elektrotechnik, Universita¨t Dortmund, D-44221 Dortmund, Germany;(3) Fachbereich Halbleitertechnik/Halbleitertechnologie, Gerhard Mercator Universita¨t Duisburg, D-47249 Duisburg, Germany;(4) Fachbereich Halbleitertechnik/Halbleitertechnologie, Gerhard Mercator Universita¨t Duisburg, D-47249 Duisburg, Germany
Abstract:Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.
Keywords:resonant tunneling devices  threshold logic  parallel counter  parallel addition
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