| 一种JTAG IP核的定制方式及其优化处理 |
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| 引用本文： | 张晓波,姜岩峰,张东. 一种JTAG IP核的定制方式及其优化处理[J]. 电子测试, 2010, 0(2): 50-55 |
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| 作者姓名： | 张晓波 姜岩峰 张东 |
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| 作者单位： | 北方工业大学信息工程学院微电子中心,北京,100041;北方工业大学信息工程学院微电子中心,北京,100041;北京自动测试技术研究所,北京,100088;北京自动测试技术研究所,北京,100088 |
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| 摘 要： | 本文介绍了一种基于IEEE1149．1标准的JTAGIP核的设计与实现,采用可综合的VerilogHDL进行描述,按设计流程进行仿真验证,并进行了系统综合验证,验证结果证实了设计的可行性。同时,根据基于JTAG标准的可测试性设计（DFT,Design For Test）的特点,提出一种优化JTAG结构的改进方案。
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| 关 键 词： | JTAG DFT Verilog HDC |
Specific design of JTAG IP core |
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| Zhang Xiaobo,Jiang Yanfeng,Zhang Dong. Specific design of JTAG IP core[J]. Electronic Test, 2010, 0(2): 50-55 |
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| Authors: | Zhang Xiaobo Jiang Yanfeng Zhang Dong |
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| Affiliation: | Zhang Xiaobo Jiang Yanfeng Zhang Dong (1 Microelectronic Center, College of Information Engineering, North China University of Technology, Beijing 100144;2 ChinaBeijing Institute of Auto-Testing Technology, Beijing, 100088, China) |
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| Abstract: | A design and implementation method for JTAG IP core based on IEEE 1149.1 standard has been proposed in this paper. It is described by Verilog HDL and simulated by design process. The simulation result demonstrated the feasibility of design work. At the same time, some improvement has been made on JTAG structure. |
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| Keywords: | JTAG DFT Verilog HDC |
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