The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's

The objective of this paper is to discuss the characteristics of SOI nMOSFET's that can be exploited to clamp HBM ESD stresses and to explain the related failure modes and mechanism observed in these devices. The influence on the HBM ESD protection capability of the first order main parameter: the nMOSFET gate length is investigated. The ESD protection capability for both positive and negative polarity HBM stresses is elaborated and compared. The ESD clamping and device failure mechanisms limiting the ESD protection performance are identified.