| 一种低压智能功率集成技术 |
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| 引用本文： | 尹贤文 黄平. 一种低压智能功率集成技术[J]. 微电子学, 1994, 24(3): 19-22,26 |
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| 作者姓名： | 尹贤文 黄平 |
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| 作者单位： | 电子工业部第２４研究所 |
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| 摘 要： | 本文介绍了一种以传统多晶硅栅ＶＤＭＯＳ工艺为主的新型自隔离智能功率集成工艺技术。该技术可以将ＶＤＭＯＳ、ＨＶ－ＣＭＯＳ、ＬＶ－ＣＭＯＳ、ｎｐｎ双极晶体管、齐纳二极管、电容等器件集成在同一单片电路中。整个工艺仅１０块掩模版。结合我们研制的高边智能功率开关电路，对器件结构、特性和工艺设计考虑进行了详细的分析。
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| 关 键 词： | 智能功率集成 低压 隔离 VDMOS |
A Novel Technique for Low-Voltage Smart Power Integration |
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| Yin Xianwen and Huang Ping. A Novel Technique for Low-Voltage Smart Power Integration[J]. Microelectronics, 1994, 24(3): 19-22,26 |
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| Authors: | Yin Xianwen and Huang Ping |
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| Abstract: | A new seif-isolation technique for smart power integration based on convetional poly-Si gate VDMOS pro-cess has been developed, By using this technique,VDMOS,HV-CMOS, LV-CMOS devices,n-p-n bipolar transistors, Zen-er diods and capecitors can all be integrated on the same chip. The process requires only 10 masks. A detailed analysis ismade on the structure and characteristics of the deviee and the process considerations for the developed high-side smartpower switching circuits are also presented. |
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| Keywords: | Smart power integration High-side switching circuit Self-isolation |
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