Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip

The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy, in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.Holger Blume received his Dipl.-Ing. degree in electrical engineering from the University of Dortmund, Germany in 1992. From 1993 to 1998 he worked as a research assistant with the Working group on Circuits and Systems for Information Processing of Prof. Dr. H. Schröder in Dortmund. There he finished his PhD on Nonlinear fault tolerant interpolation of intermediate images in 1997. In 1998 he joined the Chair of Electrical Engineering and Computer Systems of Prof. Dr. T. G. Noll at the University of Technology RWTH Aachen as a senior engineer. His main research interests are in the field of heterogeneous reconfigurable Systems on Chip for multimedia applications. Dr. Blume is chairman of the German chapter of the IEEE Solid State Circuits Society.Hendrik T. Feldkaemper received the Dipl.-Ing. degree from the University of Technology RWTH Aachen, Germany, in 1997. After half a year of employment in an industrial project at Infineon Technologies in Munich he joined the Chair of Electrical Engineering and Computer Systems (Prof. Dr. T. G. Noll), University of Technology RWTH Aachen as a research assistant. His current research interest include design space exploration for digital signal processing in ultrasound, heterogeneous reconfigurable Systems-on-Chip and VLSI CMOS design.Tobias G. Noll received the Ing. (grad.) degree in Electrical Engineering from the Fachhochschule Koblenz, Germany in 1974, the Dipl-Ing. degree in Electrical Engineering from the Technical University of Munich in 1982, and the Dr.-Ing. degree from the Ruhr-University of Bochum in 1989.From 1974 to 1976, he was with the Max-Planck-Institute of Radio Astronomy, Bonn, Germany, being active in the development of microwave waveguide and antenna components. From 1976 to 1982, he was with the MOS Integrated Circuits Department and from 1982 to 1984, the MOS-Design Team trainee program of Siemens AG, Munich. In 1984, he joined the Corporate Research and Development Department of Siemens, and since 1987, he has headed a group of laboratories concerned with the design of algorithm-specific integrated CMOS circuits for high speed digital signal processing.Since 1992, he has been a Professor for Electrical Engineering and Computer Systems with the University of Technology (RWTH), Aachen, Germany. In addition to teaching, he is involved in research activities on VLSI architectural strategies for high-speed digital signal processing, circuit concepts, and design methodologies, as well as on digital signal processing for medicine electronics.