A Compact Implementation of AES S-Box Using Evolutionary Algorithm

S-Box based on Composite field arithmetic (CFA) technology is optimized by Genetic algorithm (GA) and Cartesian genetic programming (CGP) model for re-ducing the hardware complexity. After using the CFA tech-nique to map Multiplicative inverse (MI) over GF(28) into composite field GF((24)2), the compact MI circuit over GF(24) is selected from 100 evolved circuits, and same design method is applied to the compact multipli-cation circuit over GF(22). Compared with the direct im-plementations, the areas of optimized circuits of MI over GF(24) and multiplication over GF((22)2) are reduced by 66% and 57.69%, respectively. The area reductions for MI over GF(28) and the whole of S-Box are up to 59.23%and 56.14%, separately. In 180nm 1.8V COMS technology, compared to previous works, the S-Box proposed in this paper has the minimum area and minimum power, which are 11.27% and 6.65% smaller than that of the smallest area S-Box, respectively.