一种高效的压缩Page Walk Cache结构

通用图形处理单元（GPGPU）已被广泛应用于现代高性能计算系统中。GPGPU的单指令多线程执行模型导致快表命中率较低，特别是对于那些不规则应用，需要借助PWC减少实际的页表访问次数。传统PWC中存在很多冗余信息，加之容量有限，实际效果并不理想。分析了传统PWC中的信息冗余情况，提出了一种新结构——压缩PWC。压缩PWC在保证查找开销不变的基础上，完全消除了冗余信息，压缩了空间，使PWC能够记录更多的页表访问历史，从而有效减少地址转换过程中访问页表的次数。测试结果表明，与相同容量的传统PWC相比，压缩PWC可以显著缩短虚实地址转换时间开销。

Compressed page walk cache

General-Purpose Graphics Processing Units (GPGPUs) his been widely used in modern high performance computing systems. The Single-Instruction Multi-Thread (SIMT) execution model of GPGPUs results in a lower page hit rate, and requires Page Walk Cache (PWC) to reduce the actual number of page table accesses for irregular applications. There is a lot of redundant information in the traditional PWC and the capacity is limited, so the actual effect is not good. We analyze the information redundancy in the traditional PWC and propose a new structure: Compressed PWC. Compressed PWC completely eliminates redundant information and compresses the space while keeping the same search overhead unchanged, so that PWC can record more page table access history, thereby effectively reducing the number of page table accesses during the address translation. Experimental results indicate that, compared with the traditional PWC of the same capacity, compressed PWC can significantly improve the efficiency of virtual-to-physical address translation.