High-speed GaAs SCFL divider |
| |
| Authors: | Tamura A. Sakashita T. Uenoyama T. Nishii K. Tambo T. Nagano K. Onuma T. |
| |
| Affiliation: | Matsushita Electric Industrial Co. Ltd., Central Research Laboratory, Moriguchi, Japan; |
| |
| Abstract: | A single-clocked divide-by-four circuit with a maximum operating frequency of 5.2 GHz has been developed. The circuit was fabricated using 1 ?m-gatelength high-transconductance enhancement-mode GaAs MESFETs with Pt-buried gate structure. The basic building block of the circuit is a source-coupled FET logic (SCFL) master-slave flip-flop with ECL-compatible input and output. |
| |
| Keywords: | |
|
|
