| 数字控制可编程延时单元设计技术研究 |
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| 引用本文： | 张彦龙,储鹏,文治平,于立新. 数字控制可编程延时单元设计技术研究[J]. 微电子学与计算机, 2007, 24(8): 142-144 |
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| 作者姓名： | 张彦龙 储鹏 文治平 于立新 |
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| 作者单位： | 北京微电子技术研究所,北京,100076 |
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| 摘 要： | 提出一种数字控制可编程延时单元(Digitally Controlled Programmed Delay Element,DCPDE)结构,对数字控制字可编程延时单元(DCPDE)进行了理论分析和设计方法研究。采用二进制编码控制的电流镜为延时单元提供充、放电电流,实现了信号的上升、下降沿等量延时,本单元可嵌入全数字控制的延时锁定环设计中,能够实现50%占空比420ps～920ps的双沿延时。
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| 关 键 词： | CMOS电路 延时电路 延时锁定环 延时单元 双沿延时 |
| 文章编号： | 1000-7180（2007）08-0142-03 |
| 修稿时间： | 2006-11-29 |
Design and Analysis of a Digitally Controlled Programmable Delay Element |
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| ZHANG Yan-long,CHU Peng,WEN Zhi-ping,YU Li-xin. Design and Analysis of a Digitally Controlled Programmable Delay Element[J]. Microelectronics & Computer, 2007, 24(8): 142-144 |
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| Authors: | ZHANG Yan-long CHU Peng WEN Zhi-ping YU Li-xin |
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| Affiliation: | Beijing Microelectronic Technology Institute, Beijing 100076, China |
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| Abstract: | This paper proposes a Digitally Controlled Programmable Delay Element(DCPDE) architecture,and develops the principle analysis and design procedure. The delay of the DCPDE changes monotonically with respect to the digital input vector. In the architecture,a current mirror controlled by binary digital input vector supplies the charge and discharge current for the DCPDE,obtaining equal delay at both rising and falling edge of input signal. The DCPDE can be embedded in All Digital Delay Locked loop(ADDLL),providing 50 percent duty cycle and 420ps-920ps delay time for both edges. |
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| Keywords: | CMOS integrated circuits delay circuit delay locked loop(DLL) delay element double edges |
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