Analysis of Manufacturability Factors for Analog CMOS ADC Building Blocks

In this paper, the layout of analog CMOSintegrated circuits is considered as one of the mostimportant manufacturability factors. Various layoutdesign styles are introduced and applied to the physicaldesign of latched comparators and A/D converter buildingblocks. In the following examination, post-layoutsimulation results are discussed and compared withmeasurement of the A/D circuits that were fabricated in a0.35 m digital CMOS process. It is shown in thispaper that different circuit layout styles can result insignificant differences in circuit performance.Additionally, it is shown that the layout-relatedperformance variability is attributed to statisticalprocessing variations.