An artificial neural network model of LRU-cache misses on out-of-order embedded processors |
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| Affiliation: | 1. Division of IT and Mobile Communication Business, Samsung Electronics, Suwon, Republic of Korea;2. College of ICE, Sungkyunkwan University, Suwon, Republic of Korea;1. Institute for Security in Information Technology, Technical University of Munich, Germany;2. Lab-STICC, South Brittany University, France;3. Fraunhofer Research Institution for Applied and Integrated Security (AISEC), Germany;1. State Key Laboratory of Wide Bandgap Semiconductor Technology Disciplines, Xidian University, Xi''an 710071, China;2. Institute of Natural Resources Environment and Historical Culture, Xianyang Normal University, Xianyang 712000, China;1. School of Mechanical Engineering, Tianjin University, Tianjin 300354, PR China;2. Key Laboratory of Mechanism Theory and Equipment Design of Ministry of Education, Tianjin University, Tianjin 300354, PR China |
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| Abstract: | For in-order processors, the stack distance theory is a well-known means to fast model LRU-cache behaviors . However, it cannot be applied directly on out-of-order processors due to the changing of stack distance histograms by mechanisms such as reordering executions, speculative loads, load-in-store operations and non-blocking issues.This paper proposes an Artificial Neural Network (ANN) model to fast forecast private LRU-cache behaviors on out-of-order processors. To verify our model in real commercial applications, the evaluation scenarios chosen in this paper, not only include traditional embedded benchmark suits, such as Mibench 1.0 and Mediabench II, but also embrace Android applications from Mobybench 2.0 benchmark suit as well.Compared with results from Gem5 simulations, the average root mean square error of our ANN model is less than 6% with the prediction speed increasing about 2.5× –3×. |
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