A study on the accuracy of minimum width transistor area in estimating FPGA layout area |
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| Affiliation: | 1. Computer Sciences Department, University of Jaén, Campus Las Lagunillas s/n, Jaén, 23071, Spain;2. School of Computing and Mathematics, University of Ulster, Jordanstown, BT37 0QB, U.K.;1. CEA, LIST, Laboratory of Model Driven Engineering for Embedded Systems, P.C. 174, Gif-sur-Yvette 91191, France;2. CEA, LIST, Software Reliability and Security Laboratory, P.C. 174, Gif-sur-Yvette 91191, France;3. Faculty of Computers and Information, Menofia University, Egypt;1. State Key Laboratory of Integrated Service Networks, Xidian University, Xi''an, China;2. Department of Computer Science, University of Otago, Dunedin, New Zealand;3. Science and Technology on Information Transmission and Dissemination in Communication Networks Laboratory, Shijiazhuang 050081, China;1. Pace University, New York, USA;2. Universitat Politcnica de Valncia, Valencia, Spain |
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| Abstract: | Integrating reconfigurable fabrics in SOCs requires an accurate estimation of the layout area of the reconfigurable fabrics in order to properly optimize the architectural-level design of the fabrics and accommodate early floor-planning. This work examines the accuracy of using minimum width transistor area, a widely-used area model in many previous FPGA architectural studies, in accurately predicting layout area. In particular, the layout areas of LUT multiplexers are used as a case study. We found that compared to the minimum width transistor area, the traditional metal area based stick diagrams can provide much more accurate layout area estimations. In particular, minimum width transistor area can underestimate the layout area of LUT multiplexers by as much as a factor of 2–3 while stick diagrams can achieve over 90% accuracy in layout area estimation while remaining IC-process independent. |
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