| 数字集成电路物理设计阶段的低功耗技术 |
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| 引用本文： | 桑红石,张志,袁雅婧,陈鹏.数字集成电路物理设计阶段的低功耗技术[J].微电子学与计算机,2011,28(4):73-75,80. |
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| 作者姓名： | 桑红石 张志 袁雅婧 陈鹏 |
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| 作者单位： | 华中科技大学,图像识别与人工智能研究所,多谱信息处理技术国家级重点实验室,湖北,武汉,430074 |
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| 摘 要： | 通过一个图像处理SoC的设计实例,着重讨论在物理设计阶段降低CMOS功耗的方法.该方法首先调整PAD摆放位置、调整宏单元摆放位置、优化电源规划,得到一个低电压压降版图,间接降低CMOS功耗;接着,通过规划开关活动率文件与设置功耗优化指令,直接降低CMOS功耗.最终实验结果表明此方法使CMOS功耗降低了10.92%.基于该设计流程的图像处理SoC已经通过ATE设备的测试,并且其功耗满足预期目标.
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| 关 键 词： | 集成电路 物理设计 电压降 低功耗 |
A Method of Reducing the CMOS Power During the Physical Design Stage of Digital Integrated Circuit |
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| SANG Hong-shi,ZHANG Zhi,YUAN Ya-jing,CHEN Peng.A Method of Reducing the CMOS Power During the Physical Design Stage of Digital Integrated Circuit[J].Microelectronics & Computer,2011,28(4):73-75,80. |
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| Authors: | SANG Hong-shi ZHANG Zhi YUAN Ya-jing CHEN Peng |
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| Affiliation: | SANG Hong-shi,ZHANG Zhi,YUAN Ya-jing,CHEN Peng(Institute for Pattern Recognition & Artificial Intelligence,HUST National Key Laboratory of Science&Technology on multi-spectral information processing,Wuhan 430074,China) |
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| Abstract: | The method to reduce the CMOS power during the physical design stage is disucssed in this paper,utilizing the SoC instance of an image processing design.Firstly,the placement locations of the PAD and macro cells were adjusted and the power planning was optimized.As a result,an intermediate layout with lower voltage drop is gained,which reduces the CMOS power indirectly.Secondly,the file of switching activity ratio planned and the power optimization instructions set are applied on the intermediate layout,and... |
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| Keywords: | integrated circuit physical design IR drop low power consumption |
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