An asymmetric memory cell using a C-TFT for single-bit-line SRAM's |
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Authors: | Kuriyama H. Ashida M. Tsutsumi K. Maegawa S. Maeda S. Anami K. Nishimura T. Kohno Y. Miyoshi H. |
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Affiliation: | ULSI Lab., Mitsubishi Electr. Corp., Hyogo; |
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Abstract: | This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-μm design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT |
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