Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

In this paper, we present an analytical modeling methodology for fully integrated inductively-degenerated CMOS narrow-band cascode Low Noise Amplifiers (LNA) that captures short channel transistor effects to enable rapid design space exploration in current and future process technologies. The modeling methodology captures the impact of parasitics on passive components, ESD-protection structures, and devices to accurately predict both impedance matching and noise figure. Our modeling is suitable for numerical optimization and fully automated synthesis for LNAs. The results indicate that the methodology models ESD-protected LNA circuits with 47.9% better accuracy in noise figure when compared with several current analytical modeling techniques with four orders of magnitude improvement in simulation time over circuit-level simulation. Given its speed and accuracy, the analytical modeling methodology is well-suited for design space exploration.