改进型Logistic混沌序列发生器的设计与实现

针对透地扩频通信中的Logistic混沌序列发生器占用资源高、设计复杂的问题,设计了一种基于改进型Logistic的混沌序列发生器,采用Verilog HDL语言直接进行硬件逻辑设计以节省系统资源占用,采用全并行的计算方式使混沌序列输出频率能达到系统时钟级别,以模块化编程思想完成了发生器以及测试模块的搭建。测试结果表明,该设计占用资源少,仅占用356个逻辑单元;混沌序列的输出速率可达到200 MHz;在DE0-Nano FPGA开发平台上板级验证,且输出序列的相关性能及测试统计结果均能满足混沌序列的要求。

Design and Implementation of an Improved Logistic Chaotic Sequence Generator

Aiming at the high resource occupation and complex design of Logistic chaotic sequence generator in the ground-penetrating spread spectrum communication, a chaotic sequence generator based on improved Logistic was designed. The Verilog HDL language was used to directly design the hardware logic to save system resources. The full parallel computing method was adopted to make the output frequency of the chaotic sequence reach the system clock level. The test results of the generator and the test module were completed by modular programming. The result shows that the design occupies less resources and only 356 logical units are occupied;The output rate of the sequence can reach 200 MHz;the board level verification on the DE0-Nano FPGA development platform, and the correlation performance and test statistics of the output sequence can meet the requirements of the chaotic sequence.