AES处理器S盒设计方案比较

S盒(S-BOX)是高级加密标准AES(Advanced Encryption Standard)算法实现的关键模块之一。目前主要有两种实现方案:基于查找表或者基于有限域求解。前者占用了太多的芯片面积资源,而后者时延过长,论文着重介绍了Chih-Chung Lu等提出的一种优化设计方案2],并用VerilogHDL设计了三种方案。实验表明,在面积大幅度减小的情况下该方案的时延只有少许增加,最后给出了各方案的实验结果和对比数据。

Implementation Comparison of AES Processor's S-BOX

S-BOX is one of the most important module of the Advanced Encryption Standard Algorithm. At present, there are two implementation methods, based on look-up table or finite field. However, the former takes up lots of chip area while the latter is not suitable for high speed application. In this paper, an optimized implementation of S-BOX proposed by Chih-Chung Lu2] is discussed, and all the three implementation methods by using Verilog HDL are described. Experiments indicate that chip area taken by S-BOX is significantly reduced, but not at the expense of greatly increasing the time delay. Finally, the experimental results and their comparisons are listed.