| 一种适用于相变存储器的低抖动锁相环时钟 |
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| 引用本文： | 宏潇,陈后鹏,宋志棠,蔡道林,李喜.一种适用于相变存储器的低抖动锁相环时钟[J].半导体学报,2013,34(2):025012-5. |
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| 作者姓名： | 宏潇 陈后鹏 宋志棠 蔡道林 李喜 |
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| 作者单位： | State Key Laboratory of Functional Materials for Informatics,Shanghai Institute of Micro-System and Information Technology,Chinese Academy of Sciences |
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| 基金项目： | 国家重点基础研究发展计划（2010CB934300, 2011CBA00607, 2011CB9328004）、国家集成电路重大专项（2009ZX02023-003）、国家自然科学基金(60906004, 60906003, 61006087, 61076121, 61176122, 61106001)、上海市科委（11DZ2261000,1052nm07000, 11QA1407800），中国科学院项目（20110490761） |
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| 摘 要： | A fully integrated low-jitter,precise frequency CMOS phase-locked loop(PLL) clock for the phase change memory(PCM) drive circuit is presented.The design consists of a dynamic dual-reset phase frequency detector(PFD) with high frequency acquisition,a novel low jitter charge pump,a CMOS ring oscillator based voltage-controlled oscillator(VCO),a 2nd order passive loop filter,and a digital frequency divider.The design is fabricated in 0.35μm CMOS technology and consumes 20 mW from a supply voltage of 5 V.In terms of the PCM’s program operation requirement,the output frequency range is from 1 to 140 MHz.For the 140 MHz output frequency,the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.
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| 关 键 词： | PLL PFD charge pump VCO PCM |
| 修稿时间： | 9/18/2012 1:25:30 PM |
A low jitter PLL clock used for phase change memory |
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| Hong Xiao,Chen Hongpeng,Song Zhitang,Cai Daolin and Li Xi.A low jitter PLL clock used for phase change memory[J].Chinese Journal of Semiconductors,2013,34(2):025012-5. |
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| Authors: | Hong Xiao Chen Hongpeng Song Zhitang Cai Daolin and Li Xi |
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| Affiliation: | State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China |
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| Abstract: | |
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| Keywords: | PLL PFD charge pump VCO PCM |
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