| 10Gb/s突发模式时钟数据恢复电路设计 |
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| 引用本文： | 顾皋蔚,朱恩,林叶,刘文松. 10Gb/s突发模式时钟数据恢复电路设计[J]. 半导体学报, 2012, 33(7): 075011-5 |
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| 作者姓名： | 顾皋蔚 朱恩 林叶 刘文松 |
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| 作者单位： | 东南大学射频与光电集成电路研究所,东南大学射频与光电集成电路研究所,东南大学射频与光电集成电路研究所,东南大学射频与光电集成电路研究所 |
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| 基金项目： | 江苏科技支撑计划重点项目 |
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| 摘 要： | 突发模式的时钟数据恢复是10G EPON系统的关键技术之一。本文介绍了一种基于XNOR/XOR门的振荡器，分析了其工作原理与性能，以此为基础设计了半速率突发时钟恢复电路。设计采用SMIC 0.13?m CMOS工艺进行了流片验证，芯片面积为675?m ? 625?m。测试结果表明，该电路可以即时的实现10Gbit/s的突发数据恢复，恢复出的时钟数据符合IEEE 802.3av标准,锁定时间小于5bit。
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| 关 键 词： | 数据恢复电路 突发模式 时钟 Gb CMOS技术 IEEE标准 电路设计 振荡器 |
| 修稿时间： | 2012-02-07 |
A 10 Gb/s burst-mode clock and data recovery circuit |
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| Gu Gaowei,Zhu En,Lin Ye and Liu Wensong. A 10 Gb/s burst-mode clock and data recovery circuit[J]. Chinese Journal of Semiconductors, 2012, 33(7): 075011-5 |
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| Authors: | Gu Gaowei Zhu En Lin Ye Liu Wensong |
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| Affiliation: | Institute of RF- & OE-ICs, Southeast University,Institute of RF- & OE-ICs, Southeast University,Institute of RF- & OE-ICs, Southeast University,Institute of RF- & OE-ICs, Southeast University |
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| Abstract: | The burst-mode clock and data recovery is one of the key technologies of the 10-Gigabit Ethernet Passive Optical Networks (10G-EPON) system. In this paper, we introduced a gated oscillator based on XONR/XOR cells and illustrated its working process. A half-rate BM-CDR circuit based on the proposed oscillator is designed. The design is implemented in SMIC 0.13?m CMOS technology, occupying an area of 675?m ? 625?m. The measured results show that this circuit can recover out burst-mode clock and data which meet the IEEE standard 802.3av definitions for 10Gbit/s burst-mode data transfer, the locking time is less than 5 bits. |
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| Keywords: | 10Gigabit Ethernet passive optical networks (10G-EPON) Clock and data recovery(CDR) burst-mode (BM) gated voltage-controlled-oscillator (GVCO) Frequency locked loop (FLL) |
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