| A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology |
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| 引用本文： | 梅年松,孙瑜,陆波,潘姚华,黄煜梅,洪志良.A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology[J].半导体学报,2011(3):100-104. |
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| 作者姓名： | 梅年松 孙瑜 陆波 潘姚华 黄煜梅 洪志良 |
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| 作者单位： | State Key Laboratory of ASIC & Systems;Fudan University; |
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| 基金项目： | Project supported by the National High Technology Research and Development Program of China(No.2009AA011605) |
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| 摘 要： | This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ...
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| 关 键 词： | CMOS技术 低抖动 锁相环 GHz 低相位噪声 延时频率 抖动测量 频率偏移 |
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