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直接隧穿应力下超薄栅氧MOS器件退化
引用本文:胡仕刚,郝跃,马晓华,曹艳荣,陈炽,吴笑峰.直接隧穿应力下超薄栅氧MOS器件退化[J].半导体学报,2008,29(11):2136-2142.
作者姓名:胡仕刚  郝跃  马晓华  曹艳荣  陈炽  吴笑峰
作者单位:西安电子科技大学微电子学院 宽禁带半导体材料与器件教育部重点实验室,西安 710071;西安电子科技大学微电子学院 宽禁带半导体材料与器件教育部重点实验室,西安 710071;西安电子科技大学微电子学院 宽禁带半导体材料与器件教育部重点实验室,西安 710071;西安电子科技大学微电子学院 宽禁带半导体材料与器件教育部重点实验室,西安 710071;西安电子科技大学微电子学院 宽禁带半导体材料与器件教育部重点实验室,西安 710071;西安电子科技大学微电子学院 宽禁带半导体材料与器件教育部重点实验室,西安 710071
摘    要:研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.

关 键 词:阈值电压  界面陷阱  直接隧穿  应力感应漏电流
修稿时间:6/23/2008 3:27:53 PM

Degradation of nMOS and pMOSFETs with Ultrathin Gate Oxide Under DT Stress
Hu Shigang,Hao Yue,Ma Xiaohu,Cao Yanrong,Chen Chi and Wu Xiaofeng.Degradation of nMOS and pMOSFETs with Ultrathin Gate Oxide Under DT Stress[J].Chinese Journal of Semiconductors,2008,29(11):2136-2142.
Authors:Hu Shigang  Hao Yue  Ma Xiaohu  Cao Yanrong  Chen Chi and Wu Xiaofeng
Affiliation:Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xi'an 710071,China;Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xi'an 710071,China;Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xi'an 710071,China;Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xi'an 710071,China;Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xi'an 710071,China;Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xi'an 710071,China
Abstract:The degradation of device parameters and the degradation of the stress induced leakage current (SILC) of thin tunnel gate oxide under constant direct-tunneling voltage stress are studied using nMOS and pMOSFETs with 1.4nm gate oxides.Experimental results show that there is a linear correlation between the degradation of the SILC and the degradation of Vth in MOSFETs during different direct-tunneling (DT) stresses.A model of tunneling assisted by interface traps and oxide trapped positive charges is developed to explain the origin of SILC during DT stress.
Keywords:threshold voltage  interface traps  direct tunneling  SILC
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