基于混合结构的一种高性能90nm CMOS逐次逼近A/D转换器

实现了一种10位2.5MS/s逐次逼近A/D转换器。在电路设计上采用了R-C混合结构D/A转换、伪差分比较结构以及低功耗电平转换方式实现。为了实现好的匹配性能，在版图布局上分别采用电阻梯伪电阻包围对策以及电容阵列共中心对称布局方式进行布局。整个A/D转换器基于90nm CMOS工艺实现，在3.3V模拟电源电压以及1.0V数字电源电压下，测得的DNL和INL分别为0.36LSB和0.69LSB。在采样频率为2.5MS/s，输入频率为1.2MHz时，测得的SFDR和ENOB分别为72.86dB和9.43bits。包括输出驱动在内，测得整个转换器的功耗为6.62mW。整个转换器的面积约为238um×214um。设计结果显示该转换器性能良好，非常适合多电源嵌入式SoC的应用。

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented.In the circuit design,an R-C hybrid architecture D/A converter,pseudo-differential comparison architecture and low power voltage level shifters are utilized.Design challenges and considerations are also discussed.In the layout design,each unit resistor is sided by dummies for good matching performance,and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error.This proposed converter is implemented based on 90 nm CMOS ...