2.4GHz带片上非平衡变压器射频前端的设计与优化

本文介绍了一种工作在2.4GHz频段的低功耗、低噪声、高线性射频接收机前端电路，该接收前端电路使用新型的带三种增益模式的LNA，并提出一种新的片上非平衡变压器优化技术。前端电路采用了直接变频结构，使用片上非平衡变压器实现低噪声放大器与下变频混频器之间的单端-差分转换，优化设计以提高前端电路的噪声性能。本文使用锗硅0.35um BiCMOS工艺，所采用的技术同样适用于CMOS工艺。前端电路总的最大转换增益为36dB；在高增益模式下的双边带噪声系数为3.8dB；低增益模式下，输入三阶交调点位12.5dBm。为了获得最大的输入动态范围，低噪声放大器采用三种可调增益模式，低增益模式使用by-pass结构，大大提高了大信号输入下接收前端的线性度。下变频混频器在输出端使用可调R-C tank，滤除带外高频杂波。混频器输出使用射极跟随器作为输出极驱动片外50ohm负载。该接收前端在2.85-V电源供电下，功耗为33mW，芯片面积为0.66mm2。

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

In this paper, a 2.4GHz low-power, low-noise, and high linear receiver front-end with low noise amplifier (LNA) and balun optimization technique is presented. Direct conversion architecture is employed for this front-end. The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer, and is optimized for best noise performance of the front-end. The circuit is implemented with 0.35um SiGe BiCMOS technology. The front-end has three gain steps for maximization of input dynamic range. The overall maximum gain is about 36dB. The double-sideband noise figure (DSB) is 3.8dB in the high gain (HG) mode, and the input referred third-order intercept point (IIP3) is 12.5dBm in the low gain (LG) mode. The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as output stage for test. The total front-end dissipates 33mw under 2.85-V supply and occupies 0.66mm2 die size.