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微波高功率双介质栅静电感应晶体管
引用本文:王永顺,李思渊,胡冬青.微波高功率双介质栅静电感应晶体管[J].半导体学报,2004,25(1).
作者姓名:王永顺  李思渊  胡冬青
作者单位:兰州大学物理科学与技术学院,静电感应器件研究所,兰州,730000
摘    要:提出了用同步外延法设计和制造具有双介质层栅结构和非饱和电流电压特性的高频高功率静电感应晶体管的关键技术.讨论了寄生栅源电容Cgs对静电感应晶体管高频功率特性的影响.描述了工艺上减小寄生电容、改善静电感应晶体管高频功率性能的主要方法和措施.成功地制造出频率在400MHz时输出功率大于20W、功率增益大于7dB、漏效率大于70%和700MHz时输出功率大于7W、功率增益大于5dB,漏效率大于50%的高性能静电感应晶体管.

关 键 词:静电感应晶体管  双介质栅  同步外延  寄生电容

A Microwave High Power Static Induction Transistor with Double Dielectrics Gate Structure
Wang Yongshun,Li Siyuan,Hu Dongqing.A Microwave High Power Static Induction Transistor with Double Dielectrics Gate Structure[J].Chinese Journal of Semiconductors,2004,25(1).
Authors:Wang Yongshun  Li Siyuan  Hu Dongqing
Abstract:The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are presented.The effects of parasitic gate-source capacitance (Cgs) on the power performance of SIT are discussed.The main methods and considerations to diminish Cgs,consequently to improve the high power performance are given.Synchronous epitaxy technology is the critical step to decrease Cgs.The 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.
Keywords:static induction transistor  double dielectrics gate  synchronous epitaxy  parasitic capacitance
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