20纳米nMOS器件中应力金属栅结构设计与薄膜工艺优化

对于如今的CMOS集成工艺，应变金属栅是关键的工艺引入应变技术（PIS,process-induced-strain）之一。在本文中，为了在20nm高K金属栅后栅工艺的nMOS器件中得到较高栅应力，我们对金属栅结构和薄膜工艺的优化进行了大量的研究。通过TCAD工具对工艺和器件的仿真，我们研究了先进应变金属栅技术对器件性能的影响。带有不同栅应力（0GPa~-6GPa）的金属栅电极被应用在器件的仿真中，与此同时，其他PIS技术，如e-SiC 和氮化物应力层也被应用于器件中。随着器件尺寸的减小，应变金属栅对器件中沟道载流子输运有巨大的提高作用。此外，一种新型的角栅电极结构被提出，角度与沟道应力的关系被研究。同时，一种新的全应变金属填充栅以及用平板型氧化铪层代替U型氧化铪层，都能够提高应变金属栅的效果。为了在金属栅中得到更大应力的薄膜，我们优化了物理汽相淀积氮化钛的工艺条件。在氮气流量大约6sccm，较高溅射功率和较薄膜厚的情况下我们得到了最大的压应力-6.5GPa。

Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices

MGS is one of key process-induced-strain (PIS) technologies for up-to-date CMOS integrations. In this paper, the optimizations to metal gate structure and film process were extensively investigated for great Metal-Gate Stress (MGS) in 20nm High-k/Metal-Gate-last (HK/MG-last) nMOS devices. The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values (0GPa~-6GPa) was implemented into the device simulation along with other traditional PIS technologies like e-SiC and nitride capping layer. The MGS demonstrated a great enhancing effect on channel carriers transporting in device as device pitch scaling down. In addition, the novel structure for tilted gate electrode was proposed and relatiohships between the tilt angle and channel stress was investigated. Also with a new method of Fully Stressed Replacement Metal Gate (FSRMG) and using plane-shape-HfO to substitute U-shape-HfO, the effect of MGS was improved. For greater film stress in metal gate, the process conditions for Physical Vapor Deposition (PVD) TiNx were optimized. The maxmium compressive stress of -6.5GPa TiNx was achieved with thinner film, greater RF power as well as about 6sccm N ratio.