一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗，提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道，每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性，提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成，面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时，ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。

Design of a dual channel 10bits pipelined SAR ADC

Abstract: In order to improve the sampling frequency and reduce the power consumption of a digital converter, a 10 bit dual channel pipelined successive approximation (SAR) / digital converter (ADC) is proposed. The proposed ADC consists of two high speed channels, each channel is pipelined SAR structure for low power and reduced area. Taking into account the chip area, operating speed and circuit complexity, the proposed second stage ADC SAR consists of 1 FLASH ADC bit and 6 SAR ADC bit. The proposed ADC is made of 45 CMOS nm process, the area is 0.16 mm2. The differential nonlinearity and integral nonlinearity of ADC are less than 0.36 minimum effective bits (LSB) and 0.67 LSB. When the power is 1.1 ADC, the maximum operating frequency of MS/s is 260 V. The operating frequency of 230 MS/s and 260 ADC of MS/s power consumption were 13.9 mW and 17.8 mW.