基于AXI4的卫星接收机DDR3多端口存储的设计

针对卫星图像实时接收与处理系统提出的实际应用需求，采用Xilinx的Virtex 6系列FPGA为平台设计实现了一种基于AXI4总线结构的多端口DDR3 SDRAM存储控制器。允许多个模块实时对单一DDR3外部存储器进行读写访问，满足现有系统中多处理模块需同时缓存各阶段卫星图像数据的需求。通过实际功能验证和ChipScope采样读写数据信号，验证了系统的可行性与可靠性，计算得出最大传输带宽达6.0GB/s、带宽利用率最高在70%-93%之间。应用AXI4总线结构，本多端口存储控制器在高速数据读写系统中具有很高的拓展应用价值。

Implantation of satellite receiver multi-port memory access to single DDR3 based on AXI4 bus

To meet the needs of real time satellite image receiving and processing system, we implanted the multi-port DDR3 SDRAM memory controller based on AXI4 bus on the platform of Xilinx Virtex 6 FPFA. Different modules are available to access to the unique DDR3 external memory in real time, which allows multiple processing modules to cache satellite images at different stages at the same time. Evaluated by Xilinx ChipScope software and the image processing results, feasibility and reliability of the system has been proved. Maximum bandwidth reaches 6.0GB/s and maximum utilization rate up to 70%-93% according to calculation. The multi-port memory controller can be used in extended high speed read & write applications with this standard AXI4 bus structure.