| 基于CPLD的面阵CMOS图像传感器的驱动时序设计 |
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| 引用本文： | 甘玉泉.基于CPLD的面阵CMOS图像传感器的驱动时序设计[J].电子器件,2009,32(3):500-503. |
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| 作者姓名： | 甘玉泉 |
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| 作者单位： | 1. 中国科学院西安光学精密机械研究所,西安,710119;中国科学院研究生院,北京,100039
2. 中国科学院西安光学精密机械研究所,西安,710119 |
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| 摘 要： | 在分析LUPA300型面阵CMOS图像传感器驱动时序关系的基础上,设计了此面阵CMOS图像传感器的驱动时序.选用CPLD器件作为硬件设计平台,试验VHDL语言对驱动时序进行了硬件描述,采用Quartus Ⅱ对所设计的驱动进行了功能仿真,并针对ALTERA公司的EPM1270T144C5进行了RTL级仿真及配置.系统测试结果表明,所设计的驱动时序可以满足面阵CMOS图像传感器LUPA300的各项驱动要求.
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| 关 键 词： | 面阵CMOS图像传感器 复杂可编程逻辑器件(CPLD) 驱动时序 |
Design of Driving Timing for Array CMOS Image Sensor Based on CPLD |
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| GAN Yuquan,GAO Wei,DONG Zhao.Design of Driving Timing for Array CMOS Image Sensor Based on CPLD[J].Journal of Electron Devices,2009,32(3):500-503. |
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| Authors: | GAN Yuquan GAO Wei DONG Zhao |
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| Abstract: | Driving schedules of LUPA300 array CMOS image sensor have been examined. The driving timing was designed for array CMOS sensor. Complex programmable logic device (CPLD) is used as hardware design platform for the sensor. The driving timing is described with VHDL. The function of the system was simulated by Quartus II and was successfully fulfilled. The design is fitted into EPM1270T144C5 (a CPLD produced by ALTERA). Experiments show that the driving timing is suitable for the high-speed CMOS image sensor. |
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| Keywords: | VHDL |
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