减少纳米MOS器件栅电流的研究分析

采用Schroedinger-Poisson方程自洽全量子求解法研究了MOS器件不同介质材料和栅结构栅电流，该模型对栅电流中的三维电流成分用行波统一地计算；对二维栅电流成分通过反型层势阱中准束缚态的隧穿率计算。模拟得出栅极电流与实验结果符合。研究结果表明，采用高愚栅介质材料、p-MOSFET或双栅结构对栅电流的减少有明显的作用，这一结果可望对器件性能作出预计并对其研制提供指导。

Reduction of Gate Current in Nanoscale MOS Devices

We use a quantum model based on self-consistent solutions to the Schroedinger-Poisson equations to investigate the reduction of gate tunneling current for nanoscale MOSFETs with different high-k materials and structures. The three-dimensional gate current component evaluation is performed by the traveling wave calculations. For the two-dimensional gate current component originated from the subbands in the inversion layers, a transmission calculation is performed. Our computational results are in very good agreement with experimental data. Various high-k materials, p-MOSFETs or double gate structures of interest have been examined and compared to evaluate the reduction of gate current in these structures. The results can be useful to provide the devices characteristics and guidance of device development.