一种低功耗Cache设计技术的研究

低功耗、高性能的cache系统设计是嵌入式DSP芯片设计的关键。本文在多媒体处理DSP芯片MD32的设计实践中，提出一种利用读／写缓冲器作为零级cache，减少对数据、指令cache的读／写次数，由于缓冲器读取功耗远远小于片上cache，从而减小cache相关功耗的方法。通过多种多媒体处理测试程序的验证，该技术可减少对指令cache或者数据cache20％～40％的读取次数，以较小芯片面积的增加换取了较大的功耗降低。

Study on the Low Power Cache Design Technique

Reduction of the power consumption of microprocessors has now become one of the most critical design concerns. On-chip cache memories dominate the chip area and the power consumption in microprocessor chips. This paper describes an architectural design technique, using Read/Write buffers to reduce the on-chip cache memories accesses activity, hence significantly reduce the power consumption of the whole chip because of the low power consumption characteristic of buffer compared with cache. In MD32 design, this technique normally reduces instruction cache access or data cache access by 20~40% showed by the simulation results of multimedia test benches.