| 超标量、超流水线定点RISC核设计 |
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| 引用本文： | 韦健,张明,周琼芳,遇岩,姚庆栋.超标量、超流水线定点RISC核设计[J].电路与系统学报,2001,6(4):56-60. |
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| 作者姓名： | 韦健 张明 周琼芳 遇岩 姚庆栋 |
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| 作者单位： | 浙江大学,信息与通信工程研究所ASIC设计研究室,浙江,杭州,310027 |
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| 基金项目： | 国家自然科学基金(69872033)，浙江省综合信息网技术重点实验室，教育部骨干教师计划资助项目 |
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| 摘 要： | 本文从开发指令级并行度ILP的角度出发，分析了超标量、超流水线处理器的体系结构特点，在此基础上给出了一个定点超标量RISC核设计。该设计采用Top-down设计方法，含三个流水执行单元，指令动态调度，实现非阻塞高速缓存non-blocking-caches机制。
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| 关 键 词： | RISC核 指令 微处理器 电路设计 |
| 文章编号： | 1007-0249(2001)04-056-05 |
| 修稿时间： | 2001年7月19日 |
The Design of RISC Core by Super-scalar and Super-pipelined Fixed-point Technique |
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| WEI Jian,ZHANG Ming,ZHOU Qiong-fang,YU Yan,YAO Qing-dong.The Design of RISC Core by Super-scalar and Super-pipelined Fixed-point Technique[J].Journal of Circuits and Systems,2001,6(4):56-60. |
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| Authors: | WEI Jian ZHANG Ming ZHOU Qiong-fang YU Yan YAO Qing-dong |
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| Abstract: | By exploiting instruction-level parallelism (ILP), the characteristics of architecture of super-scalar and super-pipelined processors are analyzed. Based on the achievement of research, a design of RISC core by super-scalar and super-pipelined technique is given. According to the proposed design, three pipelined execution units are configured by top-down methodology. Instruction dynamic scheduling and non-blocking-caches mechanism are also implemented. |
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| Keywords: | Instruction-level parallelism super-scalar super-pipelined non-blocking-cache reservation station |
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