| 使用非对称内表面氧化层的MOS管性能优化 |
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| 引用本文： | 于伟泽,尹海洲,骆志炯,朱慧珑,梁擎擎,许静. 使用非对称内表面氧化层的MOS管性能优化[J]. 微电子学, 2014, 0(1): 92-96 |
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| 作者姓名： | 于伟泽 尹海洲 骆志炯 朱慧珑 梁擎擎 许静 |
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| 作者单位： | 中国科学院微电子研究所 集成电路工艺先导中心, 北京 100029;中国科学院微电子研究所 集成电路工艺先导中心, 北京 100029;中国科学院微电子研究所 集成电路工艺先导中心, 北京 100029;中国科学院微电子研究所 集成电路工艺先导中心, 北京 100029;中国科学院微电子研究所 集成电路工艺先导中心, 北京 100029;中国科学院微电子研究所 集成电路工艺先导中心, 北京 100029 |
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| 基金项目： | 国家973计划资助项目(2011CBA00605)； 国家科技部02重大专项资助项目(2009ZX02035-02)； 中国科学院“百人计划”支持项目。 |
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| 摘 要： | 提出了一种用来提高短沟道MOS管性能的非对称内表面氧化层结构。该结构是在MOS管的源端附近生长一层厚的内表面氧化层,以抑制载流子迁移率的降低,同时,在MOS管的漏端附近生长一层薄的内表面氧化层,以抑制器件的短沟道效应。使用TCAD软件进行仿真和分析,结果显示,与对称内表面氧化层结构相比,非对称内表面氧化层结构具有更好的导通-关断特性。对器件进行优化,当源端较厚的内表面氧化层占总氧化层的比例为15%左右时,器件的性能得到最大幅度的提高。在相同的关断电流下,与对称内表面氧化层器件相比,非对称内表面氧化层器件的导通电流提高5%~15%。
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| 关 键 词： | 半导体器件 非对称内表面氧化层 短沟道效应 |
Further EOT Scaling for MOSFET with Asymmetric Interfacial Oxide Layer |
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| YU Weize,YIN Haizhou,LUO Zhijiong,ZHU Huilong,LIANG Qingqing and XU Jing. Further EOT Scaling for MOSFET with Asymmetric Interfacial Oxide Layer[J]. Microelectronics, 2014, 0(1): 92-96 |
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| Authors: | YU Weize YIN Haizhou LUO Zhijiong ZHU Huilong LIANG Qingqing XU Jing |
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| Affiliation: | Integrated Circuit Advanced Process Center, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing 100029, P. R. China;Integrated Circuit Advanced Process Center, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing 100029, P. R. China;Integrated Circuit Advanced Process Center, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing 100029, P. R. China;Integrated Circuit Advanced Process Center, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing 100029, P. R. China;Integrated Circuit Advanced Process Center, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing 100029, P. R. China;Integrated Circuit Advanced Process Center, Institute of Microelectronics, The Chinese Academy of Sciences, Beijing 100029, P. R. China |
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| Abstract: | Short-channel MOSFETs with asymmetric interfacial oxide layer was designed to improve device performance. A relatively thick interfacial oxide layer in source side was used to alleviate device performance deterioration due to mobility degradation. In the meantime, a relatively thin interfacial oxide layer in drain side allowed good control of short channel effects (SCE). TCAD simulation showed that the asymmetric structures had better Ion-Ioff characteristics than symmetric structures. Optimal percentages of thick asymmetric interfacial oxide layers were found to be about 15% to maximize device performance. Drive current of the optimized asymmetric structures was improved by 5% to 15% at various Ioff levels, compared with that of symmetric structures. |
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| Keywords: | Semiconductor device Asymmetric interfacial oxide layer Short channel effect (SCE) |
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