| 一种用于32位CPU的CPL流水线乘加器的设计 |
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| 引用本文： | 赵楠,李树国,羊性滋.一种用于32位CPU的CPL流水线乘加器的设计[J].微电子学,2004,34(6):670-674. |
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| 作者姓名： | 赵楠 李树国 羊性滋 |
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| 作者单位： | 清华大学,微电子学研究所,北京,100084 |
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| 基金项目： | 国家自然科学基金资助项目(60276016，60476015)，清华大学校基础研究基金资助项目(JC2003059) |
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| 摘 要： | 综合的32位乘加器需采用5段流水线才能满足CPU的设计指标，但这样会造成与CPU指令流水线不匹配，带来了控制复杂化。为解决这个问题，采用互补传输门逻辑(CPL)设计了用于32位CPU的高速乘加器，使其流水线段数从原来的5段缩减为与CPU指令流水线相匹配的3段，简化了控制、降低了功耗、节省了面积。
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| 关 键 词： | 乘法器 乘加器 互补传输门逻辑 Booth算法 中央处理器 |
| 文章编号： | 1004-3365(2004)06-0670-05 |
Design of a CPL-Based Pipeline Multiplier Accumulator for 32-Bit CPU |
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| ZHAO Nan,LI Shu-guo,YANG Xing-zi.Design of a CPL-Based Pipeline Multiplier Accumulator for 32-Bit CPU[J].Microelectronics,2004,34(6):670-674. |
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| Authors: | ZHAO Nan LI Shu-guo YANG Xing-zi |
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| Abstract: | To meet the specification of a CPU, a 5-stage pipeline structure is usually adopted for a synthesized multiplier accumulator, which, however, leads mismatch between MAC pipeline and instruction's pipeline, making the control logic more complex. A high-speed CPL-based multiplier accumulator circuit is presented in the paper. The circuit reduces the number of MAC pipeline stages from 5 to 3, which matches the instruction's pipeline, simplifying the control logic and cutting down both the power and chip area. |
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| Keywords: | Multiplier Multiplier accumulator circuit Complementary pass logic Booth algorithm CPU |
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