低功耗CMOS低噪声放大器的分析与设计

基于TSMC 0.18μm CMOS工艺,设计了一种低功耗约束下的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在共源晶体管的栅源间并联一个电容,以优化噪声;并引入一个电感,与级间寄生电容谐振,以提高增益;通过减小晶体管的尺寸,实现了低功耗。模拟结果表明,在2.45 GHz工作频率下,增益大于14 dB,噪声系数小于1 dB,直流功耗小于2 mW。

Analysis and Design of Low-Power CMOS LNA

A low-power CMOS LNA was designed based on TSMC's 0.18 μm CMOS technology. In this circuit, a capacitor was inserted between gate and source of common-source transistor to optimize noise figure, and an inductor resonance with inter-stage parasitic capacitor was introduced to improve gain. And low-power consumption was realized by reducing transistor size. Simulation results indicated that, operating at 2.45 GHz, the circuit achieved a gain above 14 dB and a noise figure below 1 dB with a DC power less than 2 mW.