| 一种基于RISC结构单片机的数字乘法器的设计 |
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| 引用本文： | 吴静,李树荣,姚素英,赵毅强,张生才.一种基于RISC结构单片机的数字乘法器的设计[J].微电子学,2004,34(5):593-596. |
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| 作者姓名： | 吴静 李树荣 姚素英 赵毅强 张生才 |
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| 作者单位： | 天津大学,专用集成电路设计中心,天津,300072 |
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| 基金项目： | 天津市科委基金资助项目(023107311) |
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| 摘 要： | 介绍了一种8位RISC结构单片机中乘法器的设计方法，分析了移位相加、加法器树、Booth编码一移位相加等多种乘法器的工作原理，并采用Synopsys综合工具实现了这些乘法器。综合及仿真结果表明，根据该8位RISC结构单片机特点设计的Booth编码一移位相加乘法器较之其它类型乘法器速度提高很多，而面积仅比最小的移位相加乘法器增加不到18％。从速度和面积两方面综合考虑，是较好的设计方案。
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| 关 键 词： | 单片机 RISC 乘法器 移位相加 Booth编码 |
| 文章编号： | 1004-3365(2004)05-0593-04 |
Design of a Digital Multiplier Based on an 8-Bit RISC Microcomputer |
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| WU Jing,LI Shu-rong,YAO Su-ying,ZHAO Yi-qiang,ZHANG Sheng-cai.Design of a Digital Multiplier Based on an 8-Bit RISC Microcomputer[J].Microelectronics,2004,34(5):593-596. |
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| Authors: | WU Jing LI Shu-rong YAO Su-ying ZHAO Yi-qiang ZHANG Sheng-cai |
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| Abstract: | Design methods for multipliers in an 8-bit RISC single-chip microcomputer are described. The operational principle of some multipliers, such as shifter-adder-multiplier, adder-tree-multiplier and Booth-encode-shifter-adder-multiplier, are analyzed, which are implemented using Synopsys's design tools. Results from synthesis and simulation shows that Booth-encode-shifter-adder-multiplier, which is designed to fit our 8-bit RISC microcomputer, operates much faster than others, while it is only 18% larger than the smallest shifter-adder-multiplier. |
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| Keywords: | Single-chip microcomputer RISC Multiplier Shifter-adder Booth-encode |
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