一种基于流水线DA算法的数字下变频器

数字下变频器是软件无线电接收机的关键组成部分,用于将模数转换器输出的中频信号进行下变频、抽取、滤波,变为低速基带信号,便于后级数字信号处理。针对DDC经典结构,在分布式算法、流水线技术及多速率数字信号处理技术的基础上,在Xilinx FPGA上实现了一种简单、高效的数字下变频器,并采用Matlab和Modelsim联合仿真验证。结果表明,该DDC不仅有效且无需乘法器资源,占用的各项硬件资源均较低,利于嵌入大型系统中,具有良好的工程应用性。

A Digital Down Converter Based on Pipelined DA Algorithm

Digital Down converter(DDC), as the key part of software defined radio receivers, is used to implement frequency down-conversion, decimation, as well as filtering of intermediate frequency signals from the output of analog-to-digital converters, so as to obtain baseband signals at low sample rate and to benefit the following digital signal processing(DSP). Aiming at the conventional DDC structures, an optimized simple and efficient DDC architecture was proposed and implemented on Xilinx FPGA based on the distribute arithmetic(DA), pipelining and multirate digital signal processing technology. It was simulated by Matlab and Modelsim. Results showed that the multiplier-less DDC was efficient and resource-saving, which was easy to be embedded into the large systems. It had outstanding performances on engineering applicability.