一种基于注入锁定环形振荡器的时钟产生电路

提出了一种基于谐波注入锁定数控环形振荡器的时钟产生电路。采用注入锁定技术,极大地抑制了环形振荡器的相位噪声。在频率调谐环路关断的情况下,数控式振荡器可以正常工作,与需要一直工作的锁相环相比,大大节省了功耗。分析了电路的参考杂散性能。在65 nm CMOS工艺下进行流片测试,芯片的面积约为0.2 mm²。测试结果表明,设计的时钟产生电路工作在600 MHz时,1 MHz频偏处的相位噪声为-132 dBc/Hz,在1 V的电源电压下仅消耗了5 mA的电流。

A Clock Generator Based on Injection-Locked Ring Oscillator

A low power, low noise clock generator based on sub-harmonic injection-locked digitally controlled ring oscillator(SILDRO) was proposed. By employing the injection locking technique, the phase noise of the ring oscillator had been greatly suppressed. Digitally controlled ring oscillator kept working properly when the frequency tuning loop was turned off, so the power consumption was greatly saved compared with that of the normal PLL whose loop needed to be always on. Spur performance had been analyzed. Fabricated in 65 nm CMOS technology, the die area was about 0.2 mm². Measurement result showed the SILDRO based clock generator achieved a phase noise performance of-132 dBc/Hz @ 1 MHz when working at 600 MHz, and it consumed only 5 mA current at 1 V supply.