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5位高速低功耗Binary-Search模数转换器
引用本文:赵汝法,熊德宇,王巍,张定冬,张珊,袁军,杨正琳,李俊峰.5位高速低功耗Binary-Search模数转换器[J].微电子学,2022,52(2):289-294.
作者姓名:赵汝法  熊德宇  王巍  张定冬  张珊  袁军  杨正琳  李俊峰
作者单位:重庆邮电大学 光电工程学院/国际半导体学院, 重庆 400065;中国科学院微电子研究所 集成电路先导工艺研发中心, 北京 100029
基金项目:重庆市科技局产业化项目(cstc2018jszx-cyztzx0211;cstc2018jszx-cyztzX0048;cstc2018jszx-cyztzx0217);重庆市教育委员会科学技术研究计划项目(KJQN201800628)
摘    要:基于65 nm CMOS工艺,设计了一种高速低功耗二分搜索算法(Binary-Search)模数转换器(ADC)。与传统Binary-Search结构相比,该ADC的比较器采用两级动态前置放大器和一级动态闩锁器组合构成,减小了静态电流,得到极低的功耗;失调电压降低到不会引起判决误差,省去了外接的数字校准模块。因此,芯片面积减小,避免了校准模块拖慢比较器的工作速度。后仿结果表明,当采样频率为1 GHz时,该Binary-Search ADC的有效位达4.59 bit,功耗仅1.57 mW。

关 键 词:模数转换器    二分搜索算法    全动态结构
收稿时间:2021/10/8 0:00:00

A 5 bit High Speed and Low Power Binary-Search ADC
CHIO U-Fat,XIONG Deyu,WANG Wei,ZHANG Dingdong,ZHANG Shan,YUAN Jun,YANG Zhenglin,LI Junfeng.A 5 bit High Speed and Low Power Binary-Search ADC[J].Microelectronics,2022,52(2):289-294.
Authors:CHIO U-Fat  XIONG Deyu  WANG Wei  ZHANG Dingdong  ZHANG Shan  YUAN Jun  YANG Zhenglin  LI Junfeng
Affiliation:Optoelec.Engineer.College / Int.Semicond.College, Chongqing Univ.of Posts and Telecomm., Chongqing 400065, P.R.China; Integrated Circuit Advanced Process R&D Center, Institute of Microelec., Chinese Academy of Sci., Beijing 100029, P.R.China
Abstract:A high speed and low power binary-search ADC was designed in a 65 nm CMOS technology. Compared with the traditional binary-search architecture, the employed comparator was composed of a two-stage dynamic preamplifier and a one-stage dynamic latch, which reduced the static current and achieved extremely low power consumption. The offset voltage was reduced to a level that do not cause decision error, and the external digital calibration module was omitted. As a result, the chip area was reduced, and calibration accessories were avoided to slow down the comparator. The post-simulation results showed that the effective bit of the binary-search ADC reached 4.59 bit, and the power consumption was only 1.57 mW at 1 GHz sampling frequency.
Keywords:
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